A spatial Cache Locality visualizer simulation demonstrating how the CPU fetches a 32-byte cache line of 64-bit float values(i.e. 8-byte each) at once inside the L1 D-cache.
So that if it has to access sequential data next, it doesn't have to fetch it from DRAM, saving around
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Snapshot History (10)
| Date | ||||
|---|---|---|---|---|
| Jun 19 · 15:00 | 4 | +1 34 | 5 | +1.3K 25.6K |
| Jun 19 · 13:00 | 4 | +1 33 | +1 5 | +560 24.3K |
| Jun 19 · 12:00 | 4 | 32 | 4 | +953 23.7K |
| Jun 19 · 10:00 | 4 | 32 | 4 | +460 22.8K |
| Jun 19 · 09:00 | 4 | +1 32 | 4 | +463 22.3K |
| Jun 19 · 08:00 | 4 | 31 | 4 | +482 21.8K |
| Jun 19 · 07:00 | 4 | +1 31 | 4 | +462 21.4K |
| Jun 19 · 06:00 | 4 | 30 | 4 | +887 20.9K |
| Jun 19 · 04:00 | +1 4 | +1 30 | 4 | +474 20.0K |
| Jun 19 · 03:00 | +3 3 | +29 29 | +4 4 | +19.5K 19.5K |
| Jun 17 · 16:03 | 0 | 0 | 0 | 0 |